Thanks to @quilt giving me that answer to my query about PyPrime, I noticed something that could well explain why Anandtech got the bad latency results for their 9950X review.
It appears that presently, if the FCLK is not clocked to 0.67 of the data rate of the RAM (or one third of the MT/s) assuming that UCLK=MEMCLK has been set in the BIOS, then the memory performance is suboptimal, as I shall demonstrate below.
Let’s start with my “Bigger Number Better” mistake, which gave me a performance boost with my 7950X but was detrimental to my 9950X performance. I am running a RAM speed of 6200 MT/s with an FCLK of 2167 with my 9950X, and here is the PyPrime result:
I looked at the Anandtech specs for the RAM, and they were running 5600MT/s RAM, and I am pretty damned sure that the FCLK in the BIOS defaulted to 2000 instead of 1867.
This would I think account for the strange latencies that they were getting compared to a 7950X.
Are you talking about the cross-CCD latencies? Those don’t have anything to do with the RAM frequencies, and I believe the FCLK impact on it doesn’t explain at all the higher latency that happened from Zen 4 to Zen 5.
To measure cross-CCD latencies, you can use a tool like this one:
Anyhow, seems like AMD already released a fix for this within their firmware:
Again, the thest you ran is not measuring cross CCD latency whatsoever.
I gave you the proper tool to measure it. If your idea is correct, you could simply make use of it and see the latencies increasing/decreasing as you make those changes you mentioned.
