Asrock Rack ROMED8-2T bogus memory slot population

I’ve been conversing with William at Asrock Tech Support, but he doesn’t seem to know the hardware very well.

I question the Page 21 DIMM slot population suggestion for 4 sticks. It seems totally incorrect based on everything I know about motherboard memory architecture.

The table has two sticks populating the standard A1 and B1 slots on one side of the socket, nearest the cpu.

It then shows the other two sticks populating G1 and H1 on the other side of the socket, the farthest slots away from the cpu.

This would give unequal signal path lengths to the DIMMS on each side of the socket and I would think would wreak havoc with memory timings.

I also have the Asrock Rack EPYCD8 motherboard and you populate 4 sticks of memory the conventional way with A1 and B1 and E1 and F1 populated. The slots closest to the cpu on each side.

I challenged William with this observation and question but he just parrots the manual.

I think the manual is wrong. What does everyone else think?

Page 7 for the slot layout and Page 21 for the DIMM population table

Asrock Rack ROMED8-2T manual

This sounds like a job for lstopo!

You can run lstopo and get a better idea of the topology. I’d turn on NPS4 and maybe get a better lay of the land.

It might be that this layout provides better average access for the “far” chiplets. Things are a little different with better support for 6 memory channels. Is it also better for each of the 4 memory controllers in rome to have 1 dimm, or for two memory controllers to be dual channel and two memory controllers to be barren? dual channel is better most of the time BUT there are some applications where that isn’t the case.

In addition to lstopo I’d probably do some tests.

Thanks for the suggestion of ltopo. This is just a future build exercise. I bought the ROMED8-2T because Asrock Rack said they were not going to support Milan cpus on the EPCYD8 or EPCYD8-2T boards.

I have the mobo and am now waiting on my 7443P order that got bumped from in stock to now awaiting August delivery.

With only four dies in the 7443P like the 7402P I currently run, I find that NPS4 is the best setup for my hosts.

LSTOPO will be the first thing I look at once I get my cpu and can put the build together.

ah so you might be better off with a different memory layout and not realize it. with 4 chiplets the two “near” memory controllers are the ones you want iirc. Ofc do testing.

I tested with NPS1, NPS2 and NPS4. NPS4 works best with all eight channels populated.

But I intend to steal 4 16GB sticks from the 7402P host to put into the 7443P host. Turns out that I don’t need 128GB anymore for the projects I am running. 64GB will be fine.

I believe that NPS2 will be the best configuration then for 4 stick populated hosts with the near controllers in use.

I have been experimenting with measuring memory bandwidth with AIDA64 on ROMED8-2T with 7302P.

The manual is indeed incorrect; with 4 DIMMs populated as per the manual, bandwidth languishes at ~40GB/s, equivalent to dual-channel Ryzen.

With the DIMMs populated in the CD-GH slots, the pairs furthest from the socket, I see 80GB/s. For some reason, AB-EF defaults back to 40GB/s.

This is with NPS=1.

Yes, I am running NPS=1 on my four sticks in CDGH slots.
I went with the explanation of the memory population and near and far controllers with this document.

the-book-of-epyc-ram-interleaving

And I tested with the manual’s suggested population layout with MLC and I also got degraded bandwidth.

So I went with my initial thinking that CDGH or ABEF were the only logical memory configurations.

At the bottom of the document it gives you the memory population sequence drawing populating from A1-A16 and which slots that correlates to.