None of the above, the A12 just has a crapton of L1 cache so it punches above its weight.
Apple is doing something interesting with their Vortex Cores that perhaps allows them to also use execution units across those two cores or off loading some things to the NPU.
Note how the NPU is located right up against the NPU and caches.
The L1$ cache is about twice as big though. So, honestly I’m inclined to believe that this is a result of brute force optimization by cache size increase.
But holy crap Apple. What is this voodoo.
I’m so impressed I was in denial.
- This thing has 6.9Billion transistors in 83.27mm² on TSMC’s new 7nm node.
- Ryzen has 4.8Billion in 213 mm² on 12/14nm.