There’s indeed no mention of ccx anywhere, i hope they opted for a more unified L3 cash. Like 8 cores side by side and L3 next to it, wil it change IF latency duno. Or perhaps the L3 is on the controlerchip that they wil need with this chiplet design.
I’d expect them to have at least two, maybe three different I/O chip designs going forward: One for EPYC (8 ch RAM + 128 PCIe-lanes), one for regular Ryzen (2ch RAM + 24 PCIe lanes), and maybe one for Threadripper (unless they repurpose faulty EPYC ones for those - seeing as the volumes are much lower).
What about APUs? Will they also feature a separate CPU chip and a separate GPU chip? If so, it would allow AMD to create more combinations, some with bigger GPUs - especially now that there’s available power budget. I could even see a combined L4 cache/video memory HBM stack.
If CPU and GPU will be on the same die, will the I/O also be integrated for APUs - the packages would need to route video separately anyways, so does a separate I/O chip bring any cost savings?
This change to more modularity could also allow AMD to potentially offer the full 24 PCIe lanes on APUs (unless the PCIe pins are reused for video, not sure about that).
AMD could open Infinity Fabric for general use on AMD platforms, allowing devices to use it instead of PCIe (using the same pathing) to go from ~64 GB/s for PCIe4 to IF2 at ~100 GB/s…
Devices would still support PCIe 4 as a fallback. Even for first generation EPYC, the interconnects used for Socket to Socket communication can double as either IF or PCIe lanes.
I feel as though AMD is really tailoring their products to the markets they intend to hit (or vice versa), rather than Nvidia’s “make it faster and shotgun it at all use cases”.
Less energy consumption is going to be a great thing for laptops and embedded devices… like all of the gaming consoles that’ll be hitting in 2019.
Processors aimed at datacenters, GPU aimed at mobile and embedded, with their discreet add-ins and consumer CPU getting incrimental improvement as a side-effect.
I don’t think Infinity Fabric is made for that, there is quite a difference in signal distance and power consumption. But maybe there is more AMD magic in that tech than I expect.
That ends up being a BIG I/O chiplet… gains in yeilds from cores might be offset by that puppy… but I/O gates have more area and tolerance of defects in some regards.
I’m struggling with the idea that (for all its benefits) the on-package north-bridge will make single thread latency lower than IMC performance from the prior gen. Certainly it offers numerous upsides for multi-thread/core work-loads and uniformity (lower/single NUMA count), but I’m going to be doubly impressed if single core memory latency has even stayed the same. Given the doubling of cache, I think its doubtful that is the case or they’d not have needed to spend that additional area on cache.
AMD graphics had an opening last year to really sock it to NVidia and failed pretty goodly with Vega being expensive and not really in much supply. They did pretty good midrange and forced NVidia to take steps to counter act the 580’s and 570’s… so that was good, but high end was still not even close. Now NVidia is again vulnerable, the whole feature that makes their cards bonkers expensive is DOA at this time. It requires a lot of work by game makers to actually use… the opening is again available for AMD graphics to come in and become mighty with a good graphic card solution. Why do I bring this up?
Well right now Intel is firmly against the ropes… certainly not going to be knocked out but hurting. AMD is dropping body blow after body blow in the processor market. IF Navi can be worth a shit and match how good the processor products are… we could be watching a massive upheaval in computer for years to come. This is truly an exciting time to be watching computing.