I’m done trying to get you to read.
That was clipped from ~50% down the page.
I just spent about 30 minutes trying to find a slide deck for someone who doesn’t trust anandtech. What is my life?
yeah, i know but they assume - there are no specs from amd yet. except its 32core (all 4 stacks are active/hot) and 3GHz, and has 128 lanes, while they didn’t list it correctly.
https://www.anandtech.com/Gallery/Album/6398#15
Found the slide deck. Look at that image. Second to last in the slide deck. Last column. This is AMD saying 4 channels.
Also, do you have sauce on the 128 lanes?
Could, perhaps - but likely (I’d bet money on it) the TR4 boards aren’t physically wired that way, i suspect there’s perhaps unused pins in the TR4 socket, even though it is mechanically the same as EPYC (my bet is they just used the socket and retention mechanism as a parts-bin/cost-save measure and just simply didn’t hook everything up on the boards/CPU package).
Ditto for 64 vs. 128 lanes. This won’t be 128 lanes either. No point in desktop boards, and it would just be double the cost in traces, etc. to hook up.
However as per my previous post above, once you do that you may as well just buy EPYC… so i very much doubt AMD would do that. TR4 is basically just EPYC budget version for desktop. Those features will be cut.
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You underestimate manufacturers ability to trick consumers into thinking they need 16 lanes for things.
I’m running 2 GPUs, 2 4k capture cards and a couple NVMe SSDs on a 1700 just fine.
Der8auer had a video a few months back about trying to get EPYC to post in a TR4 socket. They’re physically the same, I’d like to see if the new BIOS to bring them in compliance with TR2 will allow us to run EPYC.
I really don’t think AMD is playing those games. They need to cut costs on it a little for the part to have a reason to exist along-side EPYC.
I mean, really - wouldn’t you rather prefer to say you had an EPYC (epic) CPU in your desktop - if it was basically the exact same part? 
yeah thats the config of the machines they ran demo on, but that doesn’t mean it won’t get a new mobo or bios update to support 8-chan later-down the road on actual release.
/ looking 4 the 128 lanes; i think it was the amd rep stating it… not sure atm; if i don’t find within next 10min lets just say its 64lanes, until they actually release specs.
I suspect (personally) that if Der8auer managed to get an EPYC to post (i did see that video…) it would have half its lanes and memory channels unusable (board not wired for it :D)
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i could see them disabling in bios the additional memory channels or something - but i don’t see the point. Or maybe using damaged stacks with broken memory controllers?
in terms of 64/128 lanes not necessarily, you can make couple 32x lanes or use of pci-e “4” cheating it a lil. Possible it just needed bios patch to allow for it - der8auer epyc on x399 - seen that stuff happen with sandy xeons.
The entire point of that is to upsell. EPYC costs more than TR. It’s just good for them to leave them nerfed.
I’m not entirely sure what you mean by that. PCIe 4 isn’t ready yet see footnote, and 32x is completely unnecessary (I’m assuming you’re talking about a slot on the board)
EDIT: I stand corrected. It is ready, I thought it was still delayed. Bandwidth utilization just isn’t there though.
I’d suggest that’s perhaps more likely. I’d definitely put money on it being cut down somewhat vs. EPYC.
Perhaps they’re failed EPYC parts where some of the infinity fabric or memory controller is broken or whatever. Apparently AMD have been getting great yields on Ryzen dies, so maybe they’re even dies from the edge of a wafer where the full fabric or memory controller was slightly out of the edge of the wafer
They did say that it can’t access all memory directly from the additional dies vs TR v1 (they need to access via a connencted die). So it’s clear the 3rd and 4th dies don’t have memory controllers wired up to memory.
Likely their PCIe access is similarly nerfed/broken/not connected…
Think about how many more dies they can use by taking the ones that have damage on either the PCIe interconnect, the memory controller, or both and using them on the TR chips.
They can probably have mid to high 80’s in terms of yield.
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tr2 will likely compete with zen2 epyc line if it has to, not to mention as a server part board x399 or x499 won’t make much sense… unless you are deploying some lil crap (which doesn’t make sense to throw hardware at in first place)
tr2 even with 8channel memory and 128 lanes, still won’t compete with epyc zen1 32core servers. Its just different class of hardware, no point of using expensive x399 or x499 boards even is running in mono-cpu configs against epyc 1 line, most uses are for vm datacenters and memory and storage support means most there - which those TR boards aren’t good in anyway.
@thro
i haven’t heard them saying that anywhere - amd rep or computex
eh?
32 core Threadripper 2, if it had all the 128 lanes and 8 channel memory IS basically an Epyc part.
Virtually the same dies (sure, 12nm, but Zen+ is almost idential with minor tweaks). Same I/O specs. Actually with the 12nm dies and minor Zen+ enhancements it would be superior to v1 of EPYC in that situation.
AMD could save a whole heap of marketing and just market EPYC instead of both Threadripper and EPYC.
edit:
thinking more - these aren’t failed EPYC dies. Because Epyc v1 is 14nm, Epyc v2 is going to be 7nm (AMD announced that IIRC).
Unless they silently updated Epyc to 12nm (or maybe we will see EPYC+?), this is something else.
but notice, that epyc line also has 8 core parts. I don’t see it harming their server market.
// if epyc goes 7nm they will use stacked dies (2x) 2.5d chips.
Ah those are basically SAN/NAS read heads 
How many people are buying 8 core server chips anymore? My company doesn’t buy anything less than 20 core parts anymore, regardless of use. It’s all about density these days.
I can write something tomorrow about why it’s going to harm server sales if you’re interested, but it seems like you don’t have a whole lot of insights into how many corners a company will cut to save a buck.
You can bet Netapp, EMC, etc. will be snapping those up for flash based storage servers. 8 cores is plenty for them, but the 128 PCIe lanes make a wicked flash + high speed networking box. For CHEAP.
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We use Ceph for our SAN, so we need lots of CPU.
Is NetApp still a thing? I hoped they died off.
Anyways. I need sleep. catch you all later.
as my point stood, epyc has 4, 8, 16, 24, 32 core configurations; ryzen/threadripper isn’t hurting their server business. I could see them giving us full thing. (cost wise their 16 core part is MSRP $750 same price as the threadripper $800.)
NetApp still a thing.
my company still runs with haswell cpu’s, and upgrading will take another 2years if not more… we just have so much hardware its hard to simply upgrade. (unfortunately we won’t get amd epyc lines cause of lack of ecosystem in ibm blade chassis)
(yeah good night its 2:30am here.)
// at this moment it looks like TR may be more expensive than the epyc 7351P 16core with 8 channels… so they definitely are not cannibalizing their lines.
$816 Epyc
$959 TR
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