I have got some issue with my rig:
MSI ACE X670E (current bios 1.B1 Agesa 1.0.8.0), 7950X (FCLK 2000MHz, PBO disabled, SOC @ 1.195V), 2x 16GB @6200 MT/s G.SKILL CL30 (stress tested with Karhu, VT3 y-cruncher, Linpack 10GB 50x etc.), 4x M.2 running Gen 4x4 (1x via CPU, 3x via Chipset), 4090 GPU, OS Win11 23H2
Every cold boot, my system shows the GPU running via x8 4.0 speeds (tested it with 3dmark as well, ~15GB/s) instead of x16 4.0. Once I reboot, everything runs as intended → x16 4.0; system will not crash or change the PCIE GPU speed once “locked”, so no “loose contact” situation, I can use it for hours.
BIOS settings (this issue happens on other BIOSes as well) have been checked of course: for MSI => PCIE_1 slot set to “AUTO”, there is no x16 force mode, only x8 + x8 for two GPUs etc. - GPU has been re-seated and PCIE contacts cleaned, incl. PCIE slot of the motherboard.
Rear I/O: Off my CPU only runs a mice (USB), keyboard + 1x printer connected via chipset.
Do you have any other large PCIe peripherals installed? [GPU / SAS-HUB / etc]
Or any other PCIe peripherals installed? [PCIe->U2, 4K Capture Card, __Gb NIC, etc]
Well, no other GPU, capture cards or NICs…but fully populated m.2 drives (3x off of chipsets, 1 off of CPU) - but that is supported while operating the one GPU (top slot, PCIE_1) @x16 4.0
If I interrupt the initial boot (after system is shutdown) via reset button, it trains the pcie link speed correctly = x16 4.0 - it may have something to do with the delay/time the motherboard+bios provides for the initial link training…but there are no options as far as i know to adjust that. Hoping to test AGESA 1.0.9.0 / 1.1.0.0 soon for the MSI ACE X670E…still not released yet.
Thanks for the hint, already done that incl. cleaning (also slot). I wonder if it might be AGESA/BIOS as this probably affects the way PCIE link training is conducted - furthermore, I’ve read about X670E’s “Adaptive link training” that allows the PCIe device and host controller to adjust the link width and speed dynamically based on the current load on the PCIe bus → could this be a cause during cold boot that impacts negotiated link width?