Alder Lake AVX-512 undocummented support with ASUS, ASRock and Gigabyte motherboards

Interesting little discovery on the part of a few media outlets regarding the intel ADL launch.

Both Anandtech and Gamer’s Nexus have found that, when installed in motherboards from the aforementioned vendors, and all E-core’s are disabled, AVX-512 support can be fully enabled on the 12900k and 12600k CPU’s P-cores (meaning 8 and 6 Saphire rapid equivalent AVX-512 cores respectively)

Intel had previously stated that this portion of the die would be fused off- it seems that this is not the case.


Yet, Gigabyte is misrepresenting the OC ability of the 12900k at 8Ghz. Just watched Derbauer’s video, and it’s a bugged CPU-Z that was allowing validating of these CPU’s with an incorrect setting in the BIOS. And Gigabyte knew it was incorrect BEFORE release, yet they went ahead with the ad spots anyway.

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Personal take:

Super happy to see the AVX 512 options being included! That and the increase in downstream bandwidth for accelerator cards (GPU’s, TPU’s, PHI?) should make this a great little simulation machine! For AVX interested people, the 12900k might (is?) irrelevant & the 12700k looks like an absolute bargain.

Disabling the e-core’s also means that we don’t have to deal with any big.LITTLE weirdness for the scheduler, and we get some extra L3 for each of the P-cores.

You’re getting 8 Sapphire rapids core’s but with VERY high clocks for very low total cost, and we’re already seeing 16GB dimms for DDR5 at not completely exorbitant pricing.

Personally thinking of OpenFOAM (CFD) simulations with a 10^8+ polygons models where you would have OpenMP/MPICH offload some of your main solvers (Say maybe P and U?) via PETSC to a CUDA/HIP/SYCL/DPCPP device, then complete all of your other solvers (Phi, Omega, K etc.) on CPU with AVX 512.

With the shear amount of bandwidth available to devices communicating via the chipset alone, when a vendor gives us a board with 3/4 x16 physical slots I can imagine a setup like:

2*x8 gen5 electrical for the accelerators (Hip Sycl CUDA DPCPP PHI etc.)

Then use the remaining slots provided by the chipset for highspeed network/storage and/or something else?
(Ideally use something like Optane for main drive? connected via the x4 CPU link)


I hadn’t heard of this… that’s kinda nuts

Seems that intel has partially acknowledged that AVX-512 is there, reiterates it as unsupported.

Intel just sent a patch in for GCC with optimizations, with this text in the header

Hi Uros,

This patch is to update mtune for alderlake.

Bootstrap is ok, and no regressions for i386/x86-64 testsuite.

OK for master?

Update mtune for alderlake, Alder Lake Intel Hybrid Technology will not support
Intel® AVX-512. ISA features such as Intel® AVX, AVX-VNNI, Intel® AVX2, and

Phoronix article: Intel Updates Alder Lake Tuning For GCC, Reaffirms No Official AVX-512 - Phoronix

Actual patch: [PATCH] x86: Update -mtune=alderlake

I was expecting people to disable the E-cores as soon as they get their hands on Alder Lake, but I didn’t expect it to be because of AVX512 :slight_smile:


Apologies for reviving the thread:

My MSI board and 12700k died the other day, currently waiting on RMA replacements.

In the meantime picked up an Asus b660 board and i3-12100, which seems to be post fuse chip unfortunately.

There’s a great gist covering the topic here: GitHub - zingaburga/alderlake_avx512: Info on enabling AVX-512 on Alder Lake